4、时钟与同步系统 (Clock & PPS)

### 4、时钟与同步系统 (Clock & PPS)

SDR 最看重时钟精度。
* **PPS (Pulse Per Second)**：`PPS_IN_EXT` (外部) 和 `PPS_IN_INT` (内部 GPSDO)。用于多台设备对齐时间。
* **codec_main_clk**：进入 FPGA 的主时钟（LVDS 差分信号），这是整个系统处理频率的基准。
* **PLL 控制**：`pll_mosi`, `pll_sclk`, `pll_lock` 负责控制板载的锁相环芯片（如 LMK04828 等）。

对应的 xdc 映射为：

```
# --- 外部与内部 1PPS (秒脉冲) 输入信号 ---
set_property -dict {PACKAGE_PIN G11 IOSTANDARD LVCMOS33} [get_ports PPS_IN_EXT] ;# 将外部PPS输入绑定到引脚G11，电平标准3.3V
set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS33} [get_ports PPS_IN_INT] ;# 将内部(通常是GPSDO)PPS输入绑定到引脚B15，电平标准3.3V

# --- 射频芯片(Codec)主时钟 ---
set_property -dict {PACKAGE_PIN AA17 IOSTANDARD LVDS} [get_ports codec_main_clk_p] ;# 射频芯片主时钟正极，采用LVDS差分标准
set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVDS} [get_ports codec_main_clk_n] ;# 射频芯片主时钟负极，采用LVDS差分标准

# --- 板载锁相环(PLL)控制总线 ---
set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS33} [get_ports pll_ce]    ;# PLL使能信号，引脚A8
set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS33} [get_ports pll_mosi]  ;# PLL SPI数据输入，引脚C9
set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS33} [get_ports pll_sclk]  ;# PLL SPI时钟信号，引脚A9
set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS33} [get_ports ref_sel]   ;# 外部参考时钟选择信号，引脚D9
set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS33} [get_ports pll_lock]  ;# PLL锁定状态指示信号，引脚D8

# --- GPSDO / GPS 模块串口通信 ---
# set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS33} [get_ports gps_rxd] ;# GPS模块的串口接收端，引脚A14，3.3V电平
# set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS33} [get_ports gps_txd] ;# GPS模块的串口发送端，引脚B14，3.3V电平
```

[p1]:https://tuchuang.beautifulzzzz.com:3000/?path=202603/vivado_24.01_install_config.png
[p2]:https://tuchuang.beautifulzzzz.com:3000/?path=202603/B210_SCH_AD9361.png        
[p3]:https://tuchuang.beautifulzzzz.com:3000/?path=202603/B210_SCH_AD9361_LINES.png        
[p4]:https://tuchuang.beautifulzzzz.com:3000/?path=202603/B210_SCH_RF_FRONT_END.png        
[p5]:https://tuchuang.beautifulzzzz.com:3000/?path=202603/B210_SCH_RF_FRONT_END_ICs.png     
[p6]:https://tuchuang.beautifulzzzz.com:3000/?path=202603/cyusb3014_bzxc_arch.png      
[p7]:https://tuchuang.beautifulzzzz.com:3000/?path=202603/cyusb3014_bzxc_arch2.png      
[p8]:https://tuchuang.beautifulzzzz.com:3000/?path=202603/cyusb3014_bzxc_arch3.png     
[p9]:https://tuchuang.beautifulzzzz.com:3000/?path=202603/B210_SCH_USB3_PHY_ICs.png        
[p10]:https://tuchuang.beautifulzzzz.com:3000/?path=202603/B210_SCH_LED_STATE.png     
[p11]:https://tuchuang.beautifulzzzz.com:3000/?path=202603/B210_SCH_CLK_SN74LVC1G3157.png     
[p12]:https://tuchuang.beautifulzzzz.com:3000/?path=202603/B210_SCH_CLK_EXT_PPS.png        
[p13]:https://tuchuang.beautifulzzzz.com:3000/?path=202603/B210_SCH_CLK_MAX_M10S_00B_01.png    
[p14]:https://tuchuang.beautifulzzzz.com:3000/?path=202603/B210_SCH_CLK_ADF4001BRUZ.png    
[p15]:https://tuchuang.beautifulzzzz.com:3000/?path=202603/B210_SCH_CLK_MAX_ADF4001_CP.png      
[p16]:https://tuchuang.beautifulzzzz.com:3000/?path=202603/B210_SCH_CLK_LDO.png
[p17]:https://tuchuang.beautifulzzzz.com:3000/?path=202603/B210_SCH_CLK_SPI_ADF4001.png           
[p18]:https://tuchuang.beautifulzzzz.com:3000/?path=202603/B210_SCH_CLK_40M23113541.png

项目简介